1. Field of the Invention
The present invention is directed to a slip state of a convolutional code in a viterbi decoding apparatus.
2. Background of the Invention
FIG. 9 shows the structure of a conventional viterbi decoding apparatus. As shown in the figure, both of a depuncture circuit 21 and a delay circuit 25 input a convolutional code CC.
First, the convolutional code CC will be described. As shown in FIG. 10, a BCC (Binary Convolutional Coder) circuit 32 implements a convolutional processing of an input data (D0, D1, D2, D3) into convolutional codes (X0, X1, X2, X3) and (Y0, Y1, Y2, Y3) to be outputted from output portions g1 and g2, respectively, using a predetermined generator polynomial where a constraint length k=5 and a coding rate R=1/2.
A puncture circuit 33 deletes a convolutional code C2 (X0, X, X2) from the inputted convolutional codes (X0, X1, X2, X3) and (Y0, Y1, Y2, Y3) on the basis of delete patterns C3 (0001) and C4(1111) to finally output a convolutional code (Y0, Y1, Y2, X3, Y3) with the coding rate of 4/5.
The convolutional code CC to be inputted into the vitervi decoding apparatus is punctured by such a circuit as shown in FIG. 10.
A depuncture circuit 21 implements a depuncture processing of the convolutional code CC into depunctured codes to be outputted from two output portions G1 and G2.
When inputting the convolutional code CC (Y0, Y1, Y2, X3, Y3) (output of the puncture circuit 33 of FIG. 10) as shown in FIG. 11, for example, the depuncture circuit 21 inserts a dummy symbol C1 (0,0,0) through the output portion G1 to output a code (0, 0, 0, X3) from the output portion G1 and (Y0, Y1, Y2, Y3) from the output portion G2. These codes, parted and outputted from the two output portions G1 and G2 with the dummy symbol inserted into where a code is deleted, are depunctured codes.
For the code depunctured by the depuncture circuit 21, a branch-metric calculation circuit 22 calculates a branch metric, and for the branch metric and a path metric, an ACS circuit 23 performs an addition, comparison, and selection. Then, a path memory 24 decodes the code using a maximum likelihood value to output a viterbi decoding data D0.
The viterbi decoding data D0 is provided to an internal recoder 26 as well as the outside. For the viterbi decoding data D0, the recoder 26 implements the same processing as in the circuit shown in FIG. 10 to output a punctured convolutional code for comparison RCC. On the other hand, the delay circuit 25 delays the convolutional code CC by the total processing time of the depuncture circuit 21, the branch-metric calculation circuit 22, the ACS circuit 23, the path memory 24 and the recoder 26 to output a delay convolutional code DCC.
Comparing the convolutional code for comparison RCC and the delay convolutional code DCC in bits, a comparator 27 outputs the comparison result to an N-bit counter 28. At this stage, if the viterbi decoding code D0 has been decoded with accuracy, the comparison result agrees; if decoded in error, the comparison result partly disagrees.
The N-bit counter 28 counts a mismatch of the comparison results of the comparator 27 to output the total number of the mismatches as an (residual) error number ERROR to a bit synchronous control circuit 29.
Comparing the error number ERROR with the threshold value TH inputted from the outside, the bit synchronous control circuit 29 outputs a signal SLIP-REQUEST to change a slip state when the error number ERROR is larger than the threshold value TH, thereby to change the present slip state of the depuncture circuit 21.
Next, the slip state of the depuncture circuit 21 will be described. Since the depuncture circuit 21 implements the depuncture processing of the convolutional code CC in 5 bits, there are five ways of synchronization depending on the bit to be taken as a head bit. The five ways are classified as slip states 1 through 5 numbered on the basis of relative positions of the bit taken as a head bit. That is, the input timing of the convolutional code CC in the depuncture circuit 21 is based on a slip state to be set (hereinafter referred to as a setting slip state).
When the setting slip state is accurate, bits Y0, Y4 and Y8 are taken as the head bit, respectively, as shown in (a) of FIG. 12. Thus, the depuncture processing can be performed with the dummy symbols "0" properly inserted. On the other hand, when the setting slip state is inaccurate, the dummy symbol cannot be properly inserted as shown in (b) through (e) of FIG. 12.
If (a) of FIG. 12 indicates the slip state 1, (b) of FIG. 12 indicates the slip state 2 where bits Y1, Y5 and Y9 are taken as the head bit, respectively; (c) of FIG. 12 indicates the slip state (3) where bits Y2, Y6 and Y10 are taken as the head bit, respectively; (d) of FIG. 12 indicates the slip state 4 where bits X3, X7 and Y11 are taken as the head bit, respectively; and (e) of FIG. 12 indicates the slip state 5 where bits Y3, Y7 and Y11 are taken as the head bit, respectively.
When the error number ERROR is larger than the threshold value TH, the bit synchronous control circuit 29 judges that the depuncture circuit 21 is not properly synchronized with the input of the convolutional code CC (the conditions of (b) through (e) of FIG. 12), and then outputs the signal SLIP-REQUEST to the depuncture circuit 21 to further change a slip state.
Receiving the signal SLIP-REQUEST to change a slip state, the depuncture circuit changes the present slip state to a different one to input the convolutional code CC for the depuncture processing.
The bit synchronous control circuit 29 of the conventional viterbi decoding apparatus judges whether the depuncture circuit 21 is properly synchronized with the input of the convolutional code CC or not by making a comparison between the error number ERROR counted during a predetermined measuring time and a predetermined threshold value TH.
However, since only one type of the threshold value number TH is available in this method, if the threshold value TH is inappropriate due to the degree of noise in the transmission path, for example, it becomes difficult to properly judge whether the depuncture circuit is synchronized with the input of the convolutional code CC or not in the bit synchronous control circuit.
Not properly setting a slip state, the depuncture circuit cannot be synchronized with the input of the convolutional code, which causes an inaccurate viterbi decoding processing.